1. Field of the Invention
The present invention relates to a semiconductor device incorporated in a power circuit.
2. Description of the Related Art
Diodes and metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) that are used in power factor correction/power factor controller (PFC) circuits of FIGS. 15A-15C and chopper circuits that are incorporated in power circuits are packaged individually and mounted on a substrate.
In a case where the diodes and the MOSFETs or IGBTs are discretely packaged, cooling fins that are attached to the rear surface of each package release heat. On the other hand, in a case where the diodes and the MOSFETs or IGBTs are surface-mount devices (SMD), the rear surfaces thereof are attached to a substrate and release heat.
In a case where a diode element 301 and a MOSFET element 401 are discretely packaged as shown in FIG. 16, a space for mounting each of these packages needs to be provided, and then cooling fins need to be attached as well. Because an anode terminal 303 of the diode element 301 and a drain terminal 403 of the MOSFET element 401 (a collector terminal in case of an IGBT element) are connected to each other by a wiring pattern 500 formed on a substrate, the wiring pattern 500 causes inductance (referred to as “wiring inductance,” hereinafter), thereby generating spike voltage due to the wiring inductance at the time of a switching operation. For this reason, a combination of a diode and a MOSFET or IGBT that has a rated voltage equal to or greater than the spike voltage needs to be selected.
As a method for reducing such a mounting space, there is a semiconductor device having a diode and a MOSFET or IGBT loaded in a single package (see Japanese Patent Application Laid-open No. 2007-294669, for example).
Patent Document 1: Japanese Patent Publication No. 2007-294669